1. Field of the Invention
The present invention relates to a video data transfer apparatus for transferring video data to a video memory, and also to a computer system having the video data transfer apparatus incorporated therein.
2. Description of the Related Art
The so-called DMA (Direct Memory Access) transfer can be used in transferring video data supplied from an external device to a video memory in a personal computer.
FIG. 39 is a block diagram showing a conventional computer system having a DMA controller for transferring video data to a video RAM. Three video memories 51R, 51G, and 51B store color data Dr, Dg, and Db for red (R), green (G), and blue (B), respectively. These color data Dr, Dg, and Db are previously binarized, for example, by the Dither Method. DMA controller 55 obtains the right of use of an address bus 53, a data bus 52, and a control bus 54 from a CPU 59, and executes real-time transfer of the binary color data Dr, Dg, and Db stored in the three video memories 51R, 51G, and 51B to video RAMs 56R, 56G, and 56B for display. The binary color data Dr, Dg, and Db thus transferred are further sent to a monitor control unit 57 from the VRAMS 56R, 56G, and 56B to display a video image on a monitor 58.
In DMA transfer, the CPU 59 sends a display start address for the VRAM 56R for the R component to the DMA controller 55 to activate the DMA controller 55. The DMA controller 55 obtains the right of use of the buses from the CPU 59; transfers the binary color data Dr of the R Component on a first line to the VRAM 56R for the R component; and returns the right of use of the buses to the CPU 59. The CPU 59 then sends a display start address for the VRAM 56G for the G component to the DMA controller 55 to activate the DMA controller 55, which transfers binary color data Dg in the same manner as for the R component. The B component is also transferred in the same manner. In transferring video data on a second line, the CPU 59 calculates and sends respective display start addresses on the second line for the VRAMs 56R, 56G, and 56B to the DMA controller 55 for successively transferring the binary color data Dr, Dg, and Db of the color components R, G, and B, respectively.
The CPU 59 calculates respective display start addresses on each line for the VRAMs 56R, 56G, and 56B and sends the addresses to the DMA controller 55 in the above manner, and the DMA controller 55 executes DMA transfer of the color data Dr, Dg, and Db on each line accordingly, whereby one field of color data is transferred to the VRAM 56. `One field` corresponds to an image covered by one-through scanning from the left upper corner to the right lower corner on the screen. In many cases, the two-to-one interlace (or interlace scanning) is performed where two fields compose an image of one frame (or one screen). In this case, the binary color data is transferred by the DMA transfer at a rate of approximately 60 fields per second to display a moving picture on the monitor 58.
One scanning period of one horizontal line is equal to 63 microsecond for NTSC (National Television System Committee) video signals. In the conventional system shown in FIG. 39, only several fields of data can be transferred in each second because the time is consumed by the CPU 59 in calculating and sending the display start addresses to the DMA controller 55, and also consumed by the DMA controller 55 in obtaining the right of use of the buses from the CPU 59 and in the DMA transfer of the binary color data Dr, Dg, and Db on each line. Especially the CPU 59 requires a relatively long time for calculation of the display start addresses and for output of the addresses to the DMA controller 55. As described above, the conventional system transfers only several fields of data per second, and cannot display a smooth moving picture accordingly.